Top Verilog Interview Questions and Answers for Job Preparation
Tejasvee Sharma
Jan 04, 2022
Here we have given the frequently asked Verilog interview questions for job interview Preparation. So, if you attending a technical job interview then you do require to prepare these Verilog Interview questions and answers. For upcoming 2022 job interviews, we have given questions for all levels i.e. freshers, intermediate, experienced to ace the job interview after preparing from these Verilog Interview Questions & Answers.
About Verilog: Verilog is a hardware description language (HDL) used in developing model electronic systems. With the help of Verilog, developers design and verification of digital circuits, analog circuits, mixed-signal circuits, and genetic circuits at a level of abstraction.
It is a Hardware Description Language (HDL) that represents a digital system like a network switch, a memory, a microprocessor, or a flip-flop. Verilog is primarily used to verify mixed-signal circuits, analog circuits, and the design of genetic circuits. Verilog is used in the design and validation of digital circuits at the register-transfer level of abstraction.
Verilog helps design mainly at these three levels of abstraction:
Register-transfer level
Behavioral level
Gate level
2. Who founded the Verilog programming language?
Prabhu Goel, Chi-Lai Huang, Phil Moorby, and Douglas Warmke have introduced the Verilog programming language between late 1983 and early 1984.
3. Explain VHDL?
VHDL stands for Very high-speed integrated circuit Hardware Description Language. This language is used to define circuits in digital systems and its model by using dataflow, structural and behavioral style of modeling.
4. Name various variants of the VHDL?
VHDL is represented by IEEE standards and has primarily two common variants:
VHDL-1987
VHDL-1993
5. Tell the use of VHDL?
VHDL is hardware describing language used to define the behavior of electronic circuits or digital circuits.
It is used to develop hardware and make test entities to validate the behavior of that hardware.
It is used as a design entry format by different EDA tools, like synthesis tools, formal verification tools, and simulation tools.
6. Are Verilog and VHDL the same?
No, Verilog and VHDL are different, and the primary difference is that Verilog is based on C language while VHDL is based on Ada and Pascal languages.
7. Explain HDL simulators?
HDL simulators are software packages used to imitate expressions written in one of the Hardware Description Languages (HDL) like Verilog, VHDL, SystemVerilog.
8. Differentiate between non-blocking and blocking in Verilog?
In Verilog, there are two types of technical assignment statements called blocking and non-blocking. You can find them as with their different assignment operators defined by the symbols = and <=.
Blocking: The blocking assignment statement is the same as older programming languages. It blocks the existing process until it is finished. It completes the whole statement in one time before the command moves on to the following statement.
Non-blocking: The non-blocking assignment statement or operator evaluates all the right-hand sides for the existing time unit and selects the left-hand sides after the time unit.
9. Explain Verilog full case statements and Verilog parallel case statements?
Verilog full case statements: These are statements in which binary patterns of every possible case expression can fit either a case item or default. If your assumed case statement does not affect a case default and is possible to find a binary case expression that doesn’t match any of the described case items, the case statement would not be viewed as full.
Verilog parallel case statements: It is a statement where it matches a case expression, just with a single case item. If you can locate a case expression that would match more than one case item, then it is called ‘overlapping case items,’ and it would be not parallel.
10. Explain PLI and its use?
PLI stands for Programming Language Interface. It is a tool that enables interfacing between Verilog programs and C language programs. This mechanism is used to access the inner databases of the simulator in the C program. By using Verilog syntax, you can use PLI to execute complex system calls. It also gives the benefit of both the parallel and hardware-related components of Verilog and the sequential progress of a C program.
11. What is the Sensitivity list?
The sensitivity list determines that when you make modifications in any one of the components in the list change, begin end statement inside it will get executed.
12. Tell the process to run blocking and non-blocking assignments?
To run the blocking assignment, use an easy method of evaluating the right-hand side equation and updating the left-hand side expression without intervening from other Verilog statements. A process of blocking assignments is to block trailing assignments until after the completion of the existing assignment. On the other hand, the procedure of performing non-blocking assignments requires two steps:
Assess the right-hand side of all non-blocking statements at the beginning of the time step.
Update the left-hand side of all non-blocking statements after the time step.
13. Differentiate between a task and a function?
A function can’t allow a task but functions are competent in allowing other functions, no events, within functions, timing control statements, or delays are permitted and in every function, there is always be at least one argument. Also, functions can only produce one value and can’t use input or output statements. Tasks can allow a function and allow additional versions of a particular task. Tasks are competent of including any statements and are allowed to use zero or more arguments, including output, or input.
14. Explain the parallel case and full case statements?
Full case statement: It is a case statement in which all potential case expressions can be fitted with case default or case items.
Parallel case statement: It is a case statement in which it is likely to fit a case expression with a single case item. If you find a case expression that would fit more than one case item, the fitting case is named an overlapping or non-parallel statement.
15. Explain transport delay and inertial delay?
Transport delay: It is a kind of delay induced by the wires that link to the gates. Because of the wire’s resistance and inductance, it slows the signal.
Inertial delay: It is the time it carries for a gate to modify its output.
16. Tell me the way to write an FSM code in Verilog?
There are four ways to write codes:
First method: where all input decoders, current state, and output decoder are merged in one procedure.
Second method: where all sequential circuits and combinational circuits are split in a different process.
Third method: where input decoder and existing state are merged and output decoder are split into other processes.
Fourth method: all three input decoders, current state, and output decoder are split into three processes.
17. In a purified combinational circuit, is it essential to note all the inputs in the sensitivity disk? If yes, why?
Yes. In a purified combinational circuit, it is essential to note all the inputs in the sensitivity disk else, you will get a pre and post-synthesis mismatch in the output.
18. Between variable and signal, which will update first?
Signals are updated first among variables and signals.
19. Explain freeze, deposit, drive, and force command in Verilog?
Freeze: This command puts a value on the signal. This value stays the same throughout the simulation and can’t be overwritten by the simulation.
Deposit: This command is used to value the signal, but hold it until it is overwritten.
Drive: This command puts a value on the signal, and if it is edited by simulation, then it will ‘resolve’ to a new value.
Force: This is a powerful Verilog command that can drive signals at any timestamp of your simulation.
20. Create a Verilog code to change the contents of two registers with and without a temporary register?
With a temporary register:
always @ (posedge clock) begin temp=b; b=a; a=temp; end
Without a temporary register:
always @ (posedge clock) begin a <= b; b <= a; end
Verilog Interview Questions & Answers for Experienced
21. Timescale 1 Ns/ 1 Ps indicate what in a Verilog code?
The timescale command is a compiler directive that can measure simulation time or wait time. The timescale / reference_time_unit determines the unit of measure for times and waits. The time_precision defines the accuracy to which the waits are rounded off.
22. Differentiate between $setup and $hold?
The $setup and $hold help in monitoring the setup and maintaining time restrictions for sequential logic. The setup time is the lowest time in which the data must come before the engaged edge of a clock signal. The wait time is the lowest time in which the data can’t modify after the engaged edge of a clock signal.
23. Which algorithm is used in creating a sine wave in Verilog?
The most effortless and efficient way to create sine waves is using CORDIC Algorithm.
24. Explain the repeat loop in Verilog?
It is used to perform loop fixed several times. It does not loop expression as we see in the loop statement. It includes constant, signal, or variable. For example, repeat(5).
25. Differentiate between == and ===?
The result of == can be 1, 0, or X. Nevertheless, the result of === can only be 0 or 1. If you compare two numbers using == and if one or both the figures have one or more bits as X, then the result would be X. But in case, if you used ===, the result would be 0 or 1. == can only be used for comparing 1s and 0s, as It can’t compare Xs. To compare Xs, you have to use ===.
26. Explain these system tasks and their purposes? $display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.
The most used these System Tasks is $display. It can display strings, expression or values of variables.
Examples are:
$display(“Hello oni”);
-– output: Hello oni
$display($time) // current simulation time.
-– output: 460
counter = 4’b10;
$display(” The count is %b”, counter);
-– output: The count is 0010
$reset resets the simulation return to time 0; $stop stops the simulator and sets it in interactive mode where the user can write commands; $finish leaves the simulator back to the operating system.
27. Mention a Verilog code for asynchronous and synchronous reset?
Synchronous reset, synchronous defines clock dependency so reset is not be available in sensitivity disk
eg: always @ (posedge clk )
begin if (reset)
. . . end
Asynchronous defines clock independency so reset is available in sensitivity list.
Eg: Always @(posedge clock or posedge reset)
begin
if (reset)
. . . end
28. Assume a triangle and on it, there are 3 ants on each corner and they are unrestricted to move along sides of the triangle, tell the probability that they will collide?
Ants can move only along the boundaries of the triangle in either direction, let’s assume one is denoted by 1 and another by 0 as there are 3 sides so a total of 8 combinations are possible when all ants are moving in the same direction they won’t collide that is 111 or 000 so the possibility of not a collision is 2/8=1/4 or collide probability is 6/8=3/4
29. Show a case example of infer priority register?
reg r;
// Priority encoded mux,
always @ (a or b or c or select2)
begin
r = c;
case (select2)
2'b00: r = a;
2'b01: r = b;
endcase
end
30. Tell the difference between Two Lines Of Verilog Code?
#5 a = b;
a = #5 b;
#5 a = b;
Wait for five-time units before doing the action for "a = b;".
a = #5 b; The value of b is computed and stowed in an internal temp register, After five-time units, assign this stored value to a.
31. Why is it that "if (2'b01 & 2'b10)..." Doesn't Run The True Case?
This is a prevalent coding error. You used the bitwise AND operator (&) where you were required to use the logical AND operator (&&).
32. Explain casex and casez statement?
In which casex denote x and z as don’t care whereas casez denote z as don’t care. Don’t cares are not permitted in case statement so casex and casez are used.
33. Explain $strobe?
It is a synchronization tool in which data is shown only after all other statements are performed, unlike $display in which performance order could be nondeterministic.
34. Explain inferring latches and how to avoid them?
Inferring latch signifies to reproduce last value when an unrecognized branch is specified. For example, to evade latches ensure that all cases are noted in case of statements if not case default is specified. In the same way, a latch is intimated in the IF statement if ELSE IF is not determined.
always @(s1 or s0 or i0 or i1 or i2 or i3) case ({s1,s0}) 2’b00 : out = i0; 2’b01 : out = i1; 2’b10 : out = i2; endcase
In this code of 4to1 multiplexer, all combinations are not analogized and the default is also not used so a latch is presumed to reproduce the previous value.
35. Explain the duty cycle?
It is the fraction of time where the signal is low or high. It defines on time of a signal. It can be denoted by D=T/P where D means duty cycle, T means time signal is active and P means a total time of the signal.
36. Explain $random?
$random is used to create random numbers to determine hidden bugs in a program. It returns a 32-bit number. When a function is called it yields a new random number each time. It can also include an argument that makes sure that the exact random number is developed each time the test is executed. The argument can be registered, integer, or time variable.
$random;
$random();
37. Explain parallel block?
In parallel block all statements are performed concurrently (i.e. not sequential) They are defined by keyword fork and join. Timing constraints can be delivered in a parallel block. Example:-
module parallel;
reg a,b,c;
initial
begin
$monitor ("%g,a=%b,b=%b,c=%b",$time,a,b,c);
fork
#1 a=0;
#5 b=1;
#10 c=0;
join
#1 $display ("%g EXIT",$time);
end
endmodule
In this code a gets 0 after 1 time unit, b after 5 time unit, c after 10 time units and EXIT after 11 time units
38. Explain $time in Verilog?
$time function is called to get the current simulation time. A time variable is a unique register data type to hold simulation time. $time returns 64bit integer value. Example:-
time curr_time;
initial
curr_time = $time;
39. Explain defparam?
Parameter values can be dominated by using the defparam keyword at the module representation. It can also modify the parameter values at various time intervals within the module. Example:-
module hello;
parameter p1 = 0;
initial
$display ("hello p1 = %d",p1);
endmodule
module Top;
defparam c1.p1 = 2,c2.p1 = 3; //Parameter values are overridden in module Top
hello c1();//module instance of hello
hello c2();
endmodule
40. Explain rise, fall, and turnoff delays?
Rise delay displays gate output transition from any value to 1
Fall delay displays gate output transition from any value to 0
Turnoff delay displays gate output transition from any value to z
has min\typ\max values. Due to the variation in IC fabrication procedure these values are used.
